ASML and TSMC have launched an industry initiative to develop a 12-inch photomask ecosystem for High-NA extreme ultraviolet lithography, with a pilot mask line targeted for 2031 and complete lithography-system readiness for advanced semiconductor production planned for 2033.
High-NA EUV will initially enter production using the semiconductor industry’s established 6-inch mask format, so the larger mask is not required for the technology’s first manufacturing deployment. The proposed transition is instead intended to improve productivity and remove some patterning constraints as High-NA is applied across more layers and larger chip designs.
A photomask carries the circuit pattern that a lithography system projects onto a semiconductor wafer. Although the resulting structures are measured in nanometres, the mask itself is a precision-manufactured substrate whose pattern accuracy, materials, flatness, defects, and handling all influence whether it can be used in high-volume production.
Doubling the nominal mask format therefore affects substantially more equipment than the lithography scanner. Mask blanks, writing systems, inspection equipment, cleaning processes, pellicles, carriers, storage, automated handling, logistics, and metrology all have to accommodate the larger substrate while preserving the accuracy required for leading-edge manufacturing.
ASML and TSMC began the initiative ahead of the SPIE BACUS conference, with other semiconductor manufacturers and supply-chain companies expressing interest in participation. The long timetable reflects the need to develop a complete manufacturing ecosystem rather than modify a single piece of equipment.
The first major objective is a 12-inch mask pilot line by 2031. Such a facility would allow manufacturers to establish processes for writing, inspection, cleaning, defect management, handling, and transport at useful scale before the format is introduced into production fabs.
ASML is then targeting readiness for 12-inch High-NA lithography systems by 2033. The two-year interval between the proposed pilot line and production-system readiness gives mask makers, equipment manufacturers, and chip producers time to stabilise processes and qualify the necessary infrastructure.
High-NA EUV increases the numerical aperture of the projection optics compared with first-generation EUV systems, improving imaging performance as semiconductor manufacturers continue reducing feature sizes. The technology is intended to support advanced patterning without requiring an excessive increase in additional process steps.
TSMC plans to introduce High-NA into high-volume manufacturing from 2030 and expects the number of layers requiring the technology to increase as advanced chips become more complex. High-performance computing and artificial-intelligence processors are among the devices pushing requirements for denser and more demanding patterning.
As High-NA usage increases, scanner productivity becomes increasingly important to fab economics. Lithography systems represent a substantial proportion of leading-edge semiconductor capital expenditure, so improving the amount of usable wafer output produced by each tool can influence both cost per wafer and the number of systems required for a given factory capacity.
The larger mask format is also intended to address stitching constraints. High-NA scanners use an anamorphic optical architecture in which reduction differs between the two scanning directions. Large chip designs may consequently require adjacent exposure fields to be combined with very high accuracy.
A larger mask can provide more pattern area and reduce the need for some of those stitched exposures. That could simplify parts of the manufacturing flow, although the benefit has to justify replacing infrastructure developed over decades around the existing mask standard.
The established 6-inch ecosystem is extensive. Semiconductor manufacturers already rely on mature networks of mask writers, blank suppliers, inspection systems, cleaning tools, transport carriers, and fab automation designed around that format.
Changing it creates a coordination problem across the industry. A mask-tool manufacturer has limited incentive to develop a new platform unless customers intend to adopt larger masks, while semiconductor producers cannot make the transition until all of the supporting equipment and materials are available in qualified form.
The 2031 pilot target gives that supply chain a common engineering milestone. Equipment companies can design compatible tools, mask producers can establish manufacturing methods, and chipmakers can evaluate the effect on throughput and patterning before committing the format to production several years later.
The programme also shows how semiconductor scaling increasingly depends on coordinated development outside the wafer fab’s core process modules. Progress at advanced nodes depends on optics, masks, light sources, resists, metrology, inspection, materials, automation, and manufacturing equipment all reaching production readiness within the same technology window.
High-NA manufacturing can therefore begin using the existing mask standard while the 12-inch ecosystem develops in parallel. The proposed pilot line in 2031 will provide the first substantial test of whether manufacturers can reproduce the accuracy, defect control, and handling performance of the mature format at twice the nominal mask size, setting up the later decision on production adoption from 2033.
