Hybrid Ising machine combines memristors and SMTJs

Hybrid Ising machine combines memristors and SMTJs

French researchers have demonstrated a hybrid nanoelectronic Ising machine prototype. The architecture couples hafnium-oxide memristors with stochastic magnetic tunnel junctions to perform intrinsic annealing for combinatorial optimisation.


Researchers from CEA-Leti, Spintec, C2N and Université Paris-Saclay have demonstrated a hybrid nanoelectronic Ising machine that combines hafnium-oxide resistive-memory devices with stochastic magnetic tunnel junctions, using the interaction between the two technologies to provide an intrinsic annealing mechanism for combinatorial optimisation.

The work, published in Nature Communications on 16 April 2026, brings together resistive random-access memory, or ReRAM, with stochastic magnetic tunnel junctions, known as SMTJs. Rather than assigning storage and variable updates entirely to conventional digital logic, the architecture uses the physical behaviour of the devices to carry out key parts of the optimisation process.

Ising machines map optimisation problems onto interacting binary variables, often described as spins. The relationships between the variables represent the constraints or costs within the problem, and their states are repeatedly updated while the machine searches for a configuration associated with a low value of the corresponding energy function.

The approach is applicable to combinatorial problems where the number of possible solutions increases rapidly as the problem grows. Examples include logistics routing, production scheduling, resource allocation, power-grid management, electronic design, and graph optimisation.

The demonstrated architecture divides two complementary functions between its nanotechnologies. The ReRAM crossbar stores multi-level coupling values representing the structure of the optimisation problem, while the SMTJs act as binary variables whose states fluctuate because of thermal noise.

Those fluctuations are central to the search process. A purely deterministic local-search system can settle into a configuration that is better than its immediate alternatives but is not the best overall solution. Controlled stochastic behaviour gives the machine an opportunity to leave those local minima and explore other configurations.

Annealing governs how much of that randomness is available during the search. A relatively high level of stochasticity early in the process encourages exploration, while reducing it later allows the system to settle into a stable configuration.

The researchers achieved that behaviour through the electrical coupling between the ReRAM network and the magnetic tunnel junctions. The read voltage applied to the resistive-memory array also influences the SMTJs; increasing the voltage progressively strengthens the effect of the stored coupling values relative to the magnetic devices’ natural fluctuations.

The same electrical parameter can therefore move the system from a highly stochastic state towards a more deterministic one. This provides intrinsic annealing without requiring a separate control operation to calculate and distribute a new randomness setting for every update step.

Louis Hutin, co-principal investigator and senior scientist at CEA-Leti, compared the process with guiding a marble across a tilted maze. The overall slope moves the marble towards a lower point, while a controlled amount of shaking allows it to escape routes that end in local dead ends before the motion gradually settles.

In the electronic system, the stochastic magnetic tunnel junctions provide that fluctuation, while their coupling with the memristor network allows its strength to change as the optimisation progresses.

The prototype was tested on two established graph-optimisation benchmarks. It consistently reached the global optimum for a 24-vertex weighted MAX-CUT problem and for a 10-vertex, three-colour graph-colouring problem, with measurements performed at room temperature and without an externally applied magnetic field.

MAX-CUT requires a graph to be divided into two groups while maximising the combined weight of the connections crossing between them. Graph colouring assigns colours to vertices while meeting constraints on connected vertices. Both provide compact optimisation problems whose known structure allows the quality of the hardware-generated solution to be assessed directly.

The present implementation updates its variables sequentially and uses external feedback for parts of the measurement and control loop. It therefore demonstrates the device interaction and annealing mechanism rather than representing a fully integrated accelerator operating at the maximum speed available from its constituent devices.

The route towards higher performance centres on tighter integration and parallel operation. Direct coupling between the crossbar and magnetic devices could reduce analogue-to-digital conversion overhead and allow larger numbers of variables to be updated concurrently.

The researchers identify nanosecond-scale switching and extensive parallelism as routes towards much faster operation in a fully integrated design. Removing repeated movement between analogue devices and external digital control would also address one of the potential energy advantages of carrying out more of the computation where the problem data is stored.

Both device families are compatible with CMOS manufacturing and can be incorporated in back-end-of-line layers above conventional transistor circuitry. That creates a route towards three-dimensional integration in which ReRAM, stochastic magnetic devices, and the electronic circuits controlling them occupy different layers of the same system.

Such integration could reduce the repeated transfer of data between separate processing and memory resources that contributes materially to energy consumption in conventional computing. In the hybrid Ising architecture, coupling values remain within the ReRAM network while the physical behaviour of the magnetic devices contributes directly to the search process.

Scaling remains the principal engineering task. Larger arrays will be needed to establish how the architecture behaves as the number of variables and interactions grows, while the control electronics will have to move closer to the nanodevices if the proposed reductions in data movement and conversion overhead are to be realised.

Performance will also need to be compared with conventional processors and alternative Ising-machine implementations. Useful acceleration depends on more than raw switching speed: energy consumed per solved problem, silicon area, solution quality, programmability, manufacturing variation, and the overhead involved in loading new optimisation problems will all affect practical deployment.

The demonstrated system establishes that ReRAM and magnetic tunnel junctions can perform complementary roles within the same working optimisation loop. Its next phase will determine whether the intrinsic annealing behaviour demonstrated on small graph benchmarks can be preserved as the architecture moves towards larger, more highly parallel hardware.


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