AnalogAI has selected Silicon Storage Technology’s memBrain SAGE intellectual property as the core inference engine for its first edge-AI processors, targeting hardware able to train and run machine-learning models locally at power levels of one watt or below.
The processor developer will combine SST’s analog compute-in-memory architecture with its own hardware-aware algorithms. Applications identified by the companies include humanoid robots, drones, and vehicles that need to respond to changing physical conditions after deployment rather than operating solely from a model trained beforehand.
The design therefore goes beyond the more common edge-AI arrangement in which inference happens locally but most model training takes place in a data centre or workstation. AnalogAI is targeting processors capable of updating their behaviour on the device as well as executing an existing model.
Local training creates a different computing problem from inference alone. The processor has to alter model parameters, retain those changes, and perform the associated calculations without moving outside the power and thermal envelope of an embedded system.
SST’s memBrain SAGE architecture addresses data movement by carrying out computation close to or within the non-volatile memory array. Neural-network workloads repeatedly move large volumes of weight data between memory and processing hardware, and that movement can consume a substantial proportion of the system’s energy.
Analog compute-in-memory attempts to reduce the traffic by allowing stored values to participate directly in matrix operations. SST combines its SuperFlash memory technology with custom arrays, converters, control circuitry, and other analogue and digital elements to provide the computing structure used by SAGE.
The company says the underlying bitcell can store up to eight bits per cell while operating at nanoamp-level currents. Those characteristics matter because the memory is not simply providing conventional non-volatile storage; its electrical behaviour forms part of the computational architecture.
Compute-in-memory is attractive for neural networks because many workloads are dominated by repeated multiply-accumulate operations. Moving portions of that computation into the memory array can improve energy efficiency, although it also introduces engineering challenges that do not appear in the same form in fully digital accelerators.
Analogue variation, noise, converter accuracy, process differences, endurance, calibration, and temperature behaviour can all affect the relationship between a stored value and the computation produced from it. Those issues become particularly important where the system is expected to learn after deployment rather than operating with a fixed, characterised model.
AnalogAI says its proprietary algorithm has been co-optimised around the hardware rather than treating the accelerator as a generic target. The objective is to exploit the efficiency of analog compute while compensating for the practical behaviour of the silicon.
The use of production-proven embedded memory also distinguishes the project from research demonstrations built around experimental devices. SST says memBrain SAGE has been developed and deployed using 40nm and 28nm foundry processes, with 22nm development on the technology roadmap.
Those are relatively mature semiconductor nodes, which can be advantageous for embedded and industrial applications where analogue circuitry, non-volatile memory, long product lifecycles, qualification, predictable supply, and cost can matter more than achieving the smallest available geometry.
The one-watt target is equally relevant outside battery-powered products. Electrical power consumed by an embedded processor becomes heat that has to be managed inside a controller, robot joint, sensor housing, drone, or vehicle electronics enclosure. Reducing compute power can therefore simplify packaging and thermal engineering even where the equipment itself is externally powered.
Industrial equipment is already shifting more AI processing towards local edge hardware, driven by latency, connectivity, resilience, and data-handling requirements. AnalogAI’s architecture extends that proposition by attempting to place model adaptation on the same local processor.
That capability could be useful where machines encounter operating conditions that are difficult to reproduce exhaustively during offline training. Robots and autonomous equipment have to deal with changing lighting, component wear, payload variation, different surfaces, sensor drift, and unplanned obstacles.
Local adaptation also creates validation questions. Equipment that changes its behaviour after commissioning may be harder to verify in applications requiring traceability, functional safety, or tightly predictable responses. The usefulness of on-device learning will therefore depend partly on how developers control when adaptation is allowed and how updated models are assessed.
AnalogAI has not published complete processor specifications, benchmark results, pricing, or a production timetable for its first SAGE-based devices. The current milestone is the choice of silicon-proven compute-in-memory IP and its integration into an architecture specifically designed around local training and inference.
Working silicon will provide the more important evidence. Measured training performance, inference throughput, model accuracy, endurance, and real power consumption will determine whether sub-one-watt adaptive AI moves from a promising semiconductor architecture into practical robots, drones, vehicles, and industrial edge equipment.
