Unified, circuit simulation workflow incorporates fast SPICE engines to accelerate hyper-convergent designs
Today’s hyper-convergent SoCs consist of larger and faster-embedded memories, analog front-end devices, and complex I/O circuits that communicate at 100Gb+ data rates with the DRAM stack connected on the same piece of silicon in a system-in-package design. These challenges associated with verifying these complex designs scale as advanced technology process nodes present increased parasitics, process variability, and reduced margins. This results in more simulations with longer runtimes at higher accuracy impacting the overall time-to-results, quality-of-results, and cost-of-results. PrimeSim Continuum addresses the systemic complexity of such hyper-convergent designs with a unified workflow of sign-off quality simulation engines tuned for analog, mixed-signal, RF, custom digital memory designs. PrimeSim Continuum uses next-generation SPICE and FastSPICE architectures and heterogeneous computing to optimize the use of CPU and GPU resources and improve time-to-results and cost of results.
Synopsys PrimeSim SPICE simulator’s next-generation architecture with unique GPU technology delivers significant performance improvements needed to perform comprehensive analysis for analog and RF design while meeting signoff accuracy requirements.
The PrimeSim Continuum solution integrates PrimeSim SPICE and PrimeSim Pro with the PrimeSim HSPICE simulator, the gold-standard signoff reference for foundation IP and signals integrity, and the PrimeSim XA simulator, the leading FastSPICE technology for SRAM and mixed-signal verification. PrimeWave delivers a seamless experience by providing a consistent and flexible environment across all PrimeSim Continuum engines optimizing design set-up, analysis, and post-processing.
The Synopsys PrimeSim Continuum solution is now available.
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