Sony Semiconductor Solutions and imec have presented a high-density backside connectivity module designed to support next generation 3D chip integration.
The approach implements sub-100nm self-aligned through-silicon via connections, enabling low-resistance and low-leakage front-to-back connections with strong overlay performance. The work was presented at the 2026 IEEE Symposium on VLSI Technology and Circuits.
Backside connectivity is becoming increasingly important as semiconductor scaling moves beyond conventional two-dimensional layout improvements. As devices become more densely integrated, chipmakers are looking for ways to shorten interconnect paths, improve power delivery, support stacking, and enable new forms of backside functionalisation.
The Sony and imec module addresses the technical demands that arise when chips are stacked or integrated across multiple active layers. Electrical connections must be extremely small, precisely aligned, and reliable enough to support advanced image sensors, logic, memory, and heterogeneous systems.
Advanced packaging and system-level integration are now central to the future of industrial electronics. Improvements in transistor density alone are no longer enough to deliver all the performance, power, and cost gains required by AI systems, edge computing, machine vision, robotics, communications, and high-reliability embedded equipment.
Europe’s semiconductor research ecosystem has been active across several of these technology routes. Work on 300mm 2D transistor integration demonstrates how imec and its partners are pushing beyond traditional silicon scaling through materials, process integration, and manufacturability studies.
The backside connectivity work belongs to the same wider shift. As chip architectures become more three-dimensional, electrical, thermal, and mechanical constraints interact more tightly. Designers have to consider device performance alongside heat removal, signal integrity, yield, wafer handling, bonding, inspection, and long-term reliability.
Image sensors are among the most important application areas for stacked semiconductor technology. Sony has long worked on architectures that separate photodiodes, logic, and memory layers to improve sensor performance. More advanced backside connectivity could support higher pixel density, faster readout, lower power, and more integrated processing close to the sensing layer.
The same principles extend into industrial machine vision, autonomous systems, medical imaging, smart infrastructure, and factory automation. These applications increasingly require sensors and processors that can handle more data at the edge, often under tight power, latency, and space constraints. Advanced 3D integration allows functions to be placed closer together, improving compactness and reducing the burden on board-level design.
Manufacturing challenges remain before research modules become broad industrial platforms. Sub-100nm via formation, alignment, defect control, wafer thinning, bonding, and metrology are difficult at production scale. Commercial adoption will depend on whether the performance benefits justify cost, yield, and integration complexity.
The direction of semiconductor development is clear, however. Competitiveness is increasingly shaped by packaging, interconnect, and integration capability, not only by front-end transistor scaling. European research institutes, equipment suppliers, materials companies, and device manufacturers all have roles in that transition.
The Sony and imec demonstration points toward chips where the vertical dimension becomes a serious design resource. Instead of relying only on shrinking planar features, engineers gain more options for sensor performance, edge processing, power efficiency, and compact integration. As industrial systems demand more intelligence closer to the point of measurement and control, those options will carry growing manufacturing value.
