Digital power management and PMBus moving into the future

Digital power ICs communicate with each other via the System Management Bus (SMBus) using the Power Management Bus (PMBus) communication protocol and the AVSBus protocol, a subset of the PMBus protocol for implementing adaptive voltage scaling. Using SMBus and PMBus-enabled devices for power conversion provides flexibility and control that is impossible with traditional analog power systems. PMBus and its related standards are developed and maintained by the System Management Interface Forum (SMIF).

PMBus has been under development for many years; the SMIF recently celebrated its 15th anniversary. AVSBus was released as part of Revision 1.3 of the PMBus standards in March 2014. The PMBus Specification Working Group is currently working on two revisions to PMBus 1.3. The first will be PMBus Revision 1.4 to remove ambiguities and add minor functionality to the existing command set. It is currently being finalized.

A more ambitious effort is also underway to produce PMBus Revision 2.0 and AVSBus Revision 2.0, which will provide a clear separation between the PMBus/AVSBus Command Sets and the SMBus physical and transport layers. This will enable PMBus to adopt additional physical and transport layers more easily in the future. Additional changes are being considered to enable increased security within the digital power communication domain.

The PMBus Application Profile Work Group is focused on several areas:

• Extending the behavior of the existing point-to-point AVSBus architecture to allow multiple slave devices on the bus, with the related command and monitoring changes.
• Define the PMBus application profile for front-end power supplies for industrial, medical, communication, and computing markets since no application profile exists. The spec will encompass AC-input, 48Vinput, HVDC-input power supplies.
• Define the characteristics of a Universal (or Neutral) file format for configuring PMBus devices from many vendors on a newly manufactured board.
• Enable PMBus uniform implementation over other physical layers (PHYs). This will be supported in the upcoming PMBus Revision 2.0 discussed above. SMBus has been the default PHY for PMBus, but some have implemented other PHYs to transmit PMBus commands over longer distances (ENET, CAN, RS485, etc.). This effort would create a way to support PMBus over other PHY implementations.

The PMBus protocol currently includes about 200 commands that can be categorized as follows:

• Configuration
  • Output voltage
  • Operating frequency
  • OVT/OCT/OTP thresholds
  • Power “good” window
  • Fault-handling mode
  • Soft start mode
  • Synchronization
  • And others
• Control
  • Enable/disable
  • Output voltage
  • Operating frequency
  • Phase throttling
  • Margining
  • And others
• Monitoring
  • Input and output voltages
  • Input and output currents
  • Duty cycle
  • Temperature
  • And others

PMBus performance validation

As a part of product validation, it’s important to validate the product’s conformance against the protocol specification to ensure the product’s interoperability. Products from Soliton and Cadence provide two examples of ways to validate PMBus performance.

Soliton’s PMBus Slave Validation Suite is an off the shelf validation tool using National Instruments’ PXI Platform, which helps validate the devices’ compliance with timing and electrical specifications of the PMBus protocol. The tool can also validate the device’s tolerance to and recovery from various PMBus faults & exceptions and provides a comprehensive set of reports. ​

Components in the PMBus Slave Validation Suite include:

• NI PXIe 657x – Digital Pattern Generation Card with the PXIe Chassis setup
• Soliton PVS Interposer Board ​
• Oscilloscope – For performing voltage measurements ​
• Soliton PMBus Slave Validation Suite Software compatible with Windows OS (Win 10)

Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for PMBus provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. The VIP for PMBus is designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels. It helps to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for PMBus runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

The VIP for PMBus supports the latest version of the PMBus specification, PMBus Specification, version 1.3.1:

• Power System Management Protocol Specification Part I – General Requirements, Transport, and Electrical Interface
• Power System Management Protocol Specification Part II – Command Language

SMBus is not exactly I²C

While SMBus is derived from I²C, there are several significant differences between the two specifications in the areas of voltages, currents, timing, protocols, and operating modes.

The I²C specification defines the input levels to be 30% and 70% of the supply voltage V_DD, which may be 5V, 3.3V, or some other value. Instead of relating the bus input levels to V_DD, SMBus defines them to be fixed at 0.8V and 2.1V. SMBus 2.0 supports V_DD ranging from 3V to 5V. SMBus 3.0 supports V_DD ranging from 1.8V to 5V.

SMBus 2.0 defines a ‘High Power’ class that includes a 4mA sink current that cannot be driven by I²C chips. The I²C-bus is rated for 3mA. SMBus ‘high power’ devices and I²C-bus devices will work together if the pull-up resistor is sized for 3mA. SMBus ‘low power’ class is rated for 350μA.

The basic SMBus clock is defined from 10- to 100-kHz, while I²C starts with 0kHz and extends up to 100kHz, 400kHz, 1MHz, or 3MHz, depending on the mode. This means that an I²C bus running at less than 10kHz will not be SMBus compliant since the SMBus devices may time out. This can vary by manufacturer, and there are SMBus devices that support lower frequencies. SMBus 3.0 adds 400kHz and 1MHz bus speeds.

In addition to the minimum bus operating frequency not found in the I²C specification, the SMBus specification also limits the maximum amount of time a master may extend the clock low time within each byte of a message (t_LOW:MEXT). There is also a limit on the total time a slave device may extend the clock low time within each message (t_LOW:SEXT).

A further SMBus restriction on the bus operation is a timeout, t_TIMEOUT, after which the bus is presumed hung, and all devices attached to the bus must reset their I/O interface and make ready to receive a START condition.

AVSBus is a specialized extension of PMBus

Adaptive voltage scaling (AVS) is a closed-loop dynamic power minimization technique. AVS control allows the voltage supplied to an IC, and therefore its power consumption, to be continuously adjusted as needed by the instantaneous workload and the parameters of individual ICs. Adaptive voltage scaling can reduce power consumption by as much as 60%.

AVSBus was originally developed at Texas Instruments (TI) as a means to implement dynamic voltage and frequency scaling (DVFS). TI offered its AVSBus technology to the SMIF. After further development by the PMBus Specification Working Group at SMIF, the AVSBus was released as Part III of PMBus Revision 1.3 in March 2014.

The 1MHz maximum bus speed for SMBus 3.0 is not adequate to implement adaptive voltage scaling for large digital ICs such as ASICs and FPGAs. The PMBus 1.3 standard using the 1MHz maximum bus speed takes 35μs to issue a voltage command, too slow to be useful for today’s FPGAs and ASICs. AVSbus speeds the communication in two ways: it pushes the maximum bus speed up to 50MHz, and it uses a fixed 32-bit frame. As a result, AVSbus can issue a “change voltage” command in 640ns.

The AVSbus extension uses a simple (only 9 standard commands) and efficient command set optimized specifically to implement adaptive voltage scaling. The main command is used to read or set the voltage, and it is fixed at 1mV/bit. It has a range of possible voltage settings from 0V to 65.535V, more than adequate for most applications.

In summary, AVSBus is an application-specific protocol to allow a powered device such as an ASIC, FPGA, or processor to control its own voltage for power savings. PMBus is an open standard protocol that defines a means of communicating with power conversion and other devices allowing effective configuration and control as well as telemetry data. Combining these protocols in a slave device is an efficient and effective solution for systems containing loads that need to implement adaptive voltage scaling.

In this series, the first FAQ, “Digital power conversion – how does that work?” considered hardware, mostly various digital controllers and communication ICs. Building on the theme of digital power management and the flexibility that PMBus supports, the final FAQ in this series will look into “Benefits software configurable power systems.”

References

Adaptive Voltage Scaling Technology, Texas Instruments
PMBus®: Power Management Defined, System Management Interface Forum
System Management Bus, Wikipedia
VIP for PMBus, Cadence Design Systems