sureCore, the embedded memory specialist, has designed a power and area efficient, high performance, multi-port, embedded memory solution for Semidynamics’ new RISC-V-based, tensor processing chip. Semidynamics is developing a high bandwidth, vector processing unit optimised for tensor processing aimed at AI applications. In order for AI to realise its full performance potential, the speed at which tensors are mathematically manipulated is critical.
To enable this, the vector compute units must be tightly coupled to a high-performance register file. Whilst this can be implemented via a standard synthesised approach, the outcome is often inefficient in terms of power and area. The sureCore solution delivers optimal and predictable performance metrics for all key parameters.
Semidynamics’ CEO, Roger Espasa, explained that sureCore was able to deliver performance exceeding 2.5GHz with compelling area and power characteristics. “Using a standard, synthesised, physical implementation flow would deliver the performance we need but at the expense of power and area,” he explained. “Achieving the optimal configuration of Power, Performance and Area (PPA) is always the key goal in realising a chip design with the right market value proposition. This is why we went to sureCore to exploit their embedded memory expertise as this is fundamental to meeting our performance goals. In fact, it is a central feature of our highly parallel architecture that necessitates multiple instantiations of the high-performance register file to deliver the performance. Effectively we de-risked a critical part of the design.”
Paul Wells, sureCore’s CEO, added, “Usually companies come to us for ultra-low power, embedded memory solutions. What we were able to demonstrate in this case is that our innovative architectures could instead be optimised for performance and still deliver compelling power and area characteristics. As I’ve been saying for some time, power is THE critical factor for many of today’s applications – even for those whose operation demands high clock frequencies. This can create serious thermal issues which can force developers to reduce performance targets. With our power efficient solutions cutting the memory power budget, which can be significant, high performance is now a real possibility.”
Roger Espasa will be talking about “Implementation of an out-of-order RISC-V Vector Unit” at the RISC-V summit that takes place December 6-8, 2021 in San Francisco, CA. His talk covers how this has been achieved and references the sureCore, high performance, multi-port, register file solution.
Related
