sureCore and Intrinsic announce collaboration to accelerate time to market for innovative ReRAM technology
SureCore and Intrinsic have announced a collaborative relationship to accelerate time to market for Intrinsic’s innovative, Resistive Random-access Memory (ReRAM) technology. Intrinsic’s ReRAM will address the challenges faced by SoC developers seeking an embedded non-volatile storage solution for 22nm and smaller nodes now that flash is no longer a viable option. The technology has many compelling advantages including flash-like density coupled with SRAM access times. A wide range of applications will be able to benefit from such a solution including automotive, medical, wearables, AI, edge-AI and AIoT.
Embedded flash memory has been the trusted non-volatile workhorse, particularly for the microcontroller space for many years now. It has allowed products to be delivered to customers with updated firmware provided via over-the-air downloads, ensuring that both bugfixes as well as new features could be provided quickly and easily. However, with the ongoing march of Moore’s law, FinFET nodes are more cost effective but it has become increasingly challenging to scale flash beyond 28nm. This is opening the gate to new memory technologies to fill the gap. The automotive market is watching particularly closely as the drive towards increased autonomy demands higher processing power and much more embedded memory.
Flash will no longer scale with logic presenting a potent challenge to developers of advanced microcontrollers. As it is not practical to build the two technologies on the same chip, vendors are pushed towards a two-chip solution, which is far from ideal from a power perspective. Intrinsic aims to solve this problem by providing a non-volatile memory that can easily be built on the same advanced process nodes as the logic. This dramatically reduces both power consumption and removes potential data bandwidth bottlenecks and latency caused by using off-chip flash memory. Its technology can read data 10x to 100x faster and write it 1000x faster than existing solutions and is fabricated using standard processing techniques at the back-end-of-line, making it less complex and less expensive than other ReRAM solutions. This, coupled with its flash-like density and its high temperature resilience, make it especially attractive.
Paul Wells, CEO of sureCore, explained, “Intrinsic has invented a breakthrough memory technology that will enable developers to exploit the density and performance of more advanced nodes and integrate its scalable non-volatile memory solution. We have years of expertise in optimising on-chip memory with our SureFIT™ Custom SRAM Design Service that has delivered bespoke optimised memory solutions tailored to meet applications needs. This has included both single instances as well as complete compilers.
“It has been a small step to extend this service to encompass Intrinsic’s ReRAM technology and exploit our design environment to deliver the associated verification and characterisation environments underpinning the value of a compiler. The use of a memory compiler is essential to maximise the commercial potential of a new memory such as ReRAM. We are delighted to be working with a fellow British memory company to help bring their novel memory technology to market. Our unique blend of memory design expertise coupled with our proprietary tool suite enable a fast track to a successful product.”
Mark Dickinson, Intrinsic’s CEO, added, “Underpinning the sureCore sureFIT service is a suite of powerful tools that will enable us to save many years of development effort had we had to create similar solutions from scratch. In addition, sureCore’s tools and techniques have been silicon proven and have been optimised over many years to deliver memories with the lowest possible power consumption and highest density. We are delighted to be able to bring these benefits to bear in the development of our ReRAM products. Both microcontrollers and evolving AI architectures using Intrinsic ReRAM will deliver higher performance at lower power envelopes than those realised using off-chip flash.”
