PCIe 6.0 verification IP enables advanced debug and compliance checking

Avery Design Systems Inc. announced the availability of major updates to the company’s flagship PCI Express (PCIe) 6.0 and PIPE 6.0 VIP solution. Avery unveiled the solution at the PCI-Sig DevCon event this week.

The solution supports the latest features and capabilities in the high-speed interconnect protocol, including a doubling of data rates compared to PCIe 5.0, to 64 GT/s speeds, its move to PAM4 encoding, and FLIT mode, the introduction of low latency FEC, and backward compatibility with all previous specification versions.

The Avery PCIe 6.0 VIP solution enables advanced debug and compliance checking and allows designers to run pre-silicon compliance test suites. The updated Avery VIP supports co-simulation using a QEMU, speeding development time with early HW-SW integration with host OS and embedded software.