Computing platform verifies network ICs prior to silicon

April 20, 2021 Editor

The Veloce hardware-assisted verification system from Siemens Digital Industries Software lets engineers verify digital IC designs while they are still software. Processing power ranges from a single board to a multi-chassis rack.

Digital IC designs such as those used in network routers and switches perform many functions and may contain more than a billion logic gates. Performing verification on silicon is costly and time consuming. Performing that verification when the IC is still in Register Transfer Level (RTL) form, however, means you can evaluate the design, make changes in software, and quickly re-run tests.

To find and make such changes, you need an environment that emulates actual conditions. To verify designs used in, say 5G fronthaul applications, you need enough computing power to run your entire RTL code under simulated input and output conditions.

The Veloce hardware-assisted verification system from Siemens Digital Industries Software consists of a family of computers that range from a single-board desktop system (Veloce proFPGA) to a chassis of computing boards (Veloce Primo) to full rack-mount systems of multiple chassis (Veloce Strato+). At the highest level, that’s supercomputing power (Figure 1).

Figure 1. The Veloce hardware-assisted verification platform from Siemens Digital Industries Software ranges from a single computing board to a rack of many boards in chassis.

The system takes RTL code from the user, wraps it in a virtual environment, and tests the design. It virtualizes the network environment’s protocols through models. “We can virtualize a complete 5G front-haul communication network including Ethernet, CPRI, eCPRI, and Open RAN” said Jean-Marie Brunet, Sr. Director Product Management/Engineering to 5G Technology World. “By having virtualized models of silicon, you can change the models as the specs change.”

For verifying network ICs, you’ll also need stimulus and that means virtualized test equipment. Figure 2 shows network testers from Keysight, Siemens, and Spirent that generate traffic based on RFC 2889 and RFC 2544. The Veloce system virtualizes those testers and adds the necessary transport protocols to put the virtual IC into its environment from which it can evaluate the virtual device under test. On the back end, the system takes the virtual waveforms from the DUT and provides test results such as dropped packets, packet latency, throughput, and bandwidth.

Figure 2. The platform emulates network traffic for an RTL design and produces test data.

In addition to emulating 5G networks, the Veloce system can verify Wi-Fi IC code at baseband. You can, of course, use the platform to verify other types of digital IC designs such as computational storage devices.

Because the Veloce system is modular, you can combine the computer chassis into systems. For example, the rack shown in both figures consists of your chassis, but you can configure smaller systems as well. According to Brunet, a rack such as those shown can handle RTL code for design of two billion gates. A single chassis, which can contain up to 16 computing boards, might handle design with under 200 million gates. A single board contains 24 processors.