Cadence unveils enhancements to the Xcelium Logic Simulator

13 August 2020

Cadence Design Systems has announced that the Xcelium Logic Simulator has been enhanced with machine learning technology (ML), called Xcelium ML, to increase verification throughput.

By using new machine learning technology and core computational software, Xcelium ML enables up to 5X faster verification closure on randomized regressions.

Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium ML learns iteratively over an entire simulation regression. It analyses patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles.

The Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation and supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator is used by most leading semiconductor companies, and a majority of companies in the hyperscale, automotive and consumer electronics segments.

“Xcelium ML is a powerful technology and a great example of the significant opportunity we have to leverage machine learning in verification,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “Logic simulation continues to be the workhorse of digital verification, and we are investing heavily in fundamental performance optimizations like Xcelium ML to deliver the highest verification throughput to customers using our flow.”

Author
Neil Tyler